1. Field of the Invention
The present invention relates to a system decoder in an optical disk reproducing device, and more particularly, to an apparatus and method for controlling a priority order of access to a memory in a digital video (or versatile) disk device.
2. Description of the Related Art
A digital video disk, as a recording medium for a digital moving picture, is an inexpensive multimedia recording medium capable of recording high quality video/audio data. Such a digital video disk can record over two hours of MPEG2 (Moving Picture Experts Group 2) digital image data.
FIG. 1 shows a known general digital video disk (DVD) reproducing device (also referred to as a “DVD player”, a “DVD reader” or simply a “DVD apparatus”). The DVD player is provided with a disk motor 160 which rotates a disk 100 at a constant linear velocity. An optical pickup 140, with a head 130, reads a digital image signal on the disk 100 and converts the digital image signal into an analog high frequency (RF) signal. The converted analog signal compensates the feature of RF frequency input through a radio frequency equalizer RF EQ and is reshaped into a pulse to generate ESM (Eight-to-Sixteen Modulation) data of a data stream via an ESM slicer 135. The ESM data is applied to a system decoder 200 and a digital phase locked loop (hereinafter referred to as “PLL”) 300, to generate a first clock phase locked with a signal reproduced from the disk 100, thereby generating a clock PLCK capable of reading the ESM data in the system decoder 200. The system decoder 200 performs demodulation, error correction and descrambling operations with respect to the ESM data, and detects a frame synchronous signal Sf which is applied to a disk drive controller 400. A memory 280, including first and second memory regions (not shown), temporarily stores the data generated from the system decoder 200 during the above stated operations. The memory 280 is typically a DRAM (Dynamic Random Access Memory).
A microcomputer 500 controls an overall operation of the DVD player, and generates a transfer control signal in response to a data transfer start signal from the audio/video decoder 600 or a ROM decoder 950.
The digital PLL 300 includes a phase comparator, a voltage controlled oscillator and a frequency demultiplier (all not shown), to generate the first clock phase-locked with the signal reproduced from the disk 100, thereby generating a clock PLCK capable of reading the ESM data in the system decoder. The disk drive controller 400 maintains the constant linear velocity of the disk revolution and performs other disk operations according to the frame synchronous signal Sf supplied from a synchronization detector (not shown) in the system decoder 200 and a clock signal supplied from a system clock generator 900, using a frequency servo and a phase servo (not shown). The system clock generator 900 generates the clocks needed by the system decoder 200.
The audio/video decoder 600 divides the data output from the system decoder 200 into audio data and video data. The demodulated audio and video data output from the audio/video decoder 600 are transferred to a speaker 970 and a monitor 960, respectively, via a digital-to-analog converter 800 and an NTSC encoder 700.
The ROM (Read Only Memory) decoder 950 is commonly supplied in a host (e.g., a personal computer) and operates according to a control of the host. The ROM decoder 950 transfers data generated from the system decoder 200 to the host based on a predetermined interfacing method.
FIG. 2, is a detailed block diagram of the system decoder 200 of the known DVD player shown in FIG. 1. The ESM data read from the digital video disk 100 is applied to the system decoder 200. The ESM data is first amplified by an amplifier 114. An ESM demodulator 115, connected to a first data bus 126, demodulates the data output by the amplifier 114. An ECC (error correction circuit) 116 connected to the first data bus 126 corrects any errors in the demodulated data output by the ESM demodulator 115. The data output from the ESM demodulator 115 and the ECC 116 are stored into a first memory (not shown) via a first memory controller 121 connected to the first data bus 126. When it is required to read or write data through access of the first memory in the ESM demodulator 115 or the error correction circuit 116, the memory controller 121 generates a control signal capable of smoothly accessing the first memory as required. Because the memory access is randomly required in the above ESM demodulator 115 or the error correction circuit 116, the memory controller 121 controls timing crash therein. A first memory refresh circuit 123, connected to the first memory controller 121, refreshes the first memory.
A descrambler 117 descrambles the error corrected data output from the ECC 116. An internal SRAM (Static Random Access Memory) 125 temporarily stores the descrambled data of the descrambler 117. A data writer 118 connected to a second data bus 127 stores the data output from the descrambler 117 into a second memory (not shown). A microcomputer memory access controller 119 connected to the second data bus 127 controls the microcomputer 500 (see FIG. 1) to access the second memory. An A/V decoder interface and DVD-ROM interface 120 connected to the second data bus 127 transmits the descrambled data stored in the second memory to the audio/video decoder 600 and/or the ROM decoder 950.
A second memory controller 122 connected to the second data bus 127 controls the data writer 118, the microcomputer memory access controller 119, and the A/V decoder interface and DVD-ROM interface 120 makes access to the second memory. A second memory refresh circuit 124 connected to the second memory controller 122 refreshes the second memory. A microcomputer interface controller 111 forms an interfacing between the microcomputer 500 (see FIG. 1) and the system decoder 200. A microcomputer register 112 connected to the first and second data buses 126 and 127 receives data output from the microcomputer interface controller 111 to store control signals for controlling each device 115-125 of the system decoder 200, and temporarily stores state information generated from each of the above stated devices to provide the microcomputer 500 with the state information. A priority order controller 113 controls a priority order of access to the first memory, the second memory and the SRAM 125 in response to access request signals respectively from the first memory refresh circuit 123, the ESM demodulator 115, the error correction circuit 116, the descrambler 117, the data writer 118, the microcomputer memory access controller 119, the A/V decoder interface and DVD-ROM interface 120, and the second memory refresh circuit 124.
As can be appreciated from the above descriptions, the prior art system decoder 200 includes three memories (i.e., the first and second memories, and the internal SRAM 125) for storing data from each device 115-125, thereby resulting in an increase of size and higher manufacturing costs. Therefore, a reduction in the number of memories is needed to improve the operation of the priority order controller 113 and the DVD player as a whole.